Question

The kernel Makefile init the variables like KBUILD_OUTPUT outside any target’s make process. The code is like this:

ifeq ("$(origin O)", "command line")
  KBUILD_OUTPUT := $(O)
endif

But when I try to output KBUILD_OUTPUT in the target’s make process, for example, the target help, I find it is not defined. The code I modified is like this:

help:
    @echo 'KBUILD_OUTPUT: ${KBUILD_OUTPUT}'

When I execute make O=../build help, the KBUILD_OUTPUT variable is empty. I want to know when will it init?

Thanks a lot.

Update

However, when I just write a Makefile with this:

ifeq ("$(origin O)", "command line")
  KBUILD_OUTPUT := $(O)
endif

help:
    @echo 'KBUILD_OUTPUT: ${KBUILD_OUTPUT}'

Then I run make O=../build help, I will see KBUILD_OUTPUT: ../build.

Is there anything special in kernel’s Makefile?

Answer 1

The kernel make process is a bit more complicated than most makes. The main kernel makefile will recursively call itself (that is, it calls make specifying itself as the makefile, but giving different target sets). Because of this, large portions of the main kernel Makefile has conditionals around them, some parts meant to be executed when the Make is first invoked, and others which are meant to be executed when the makefile is invoked as a child of itself. The code you are quoting, is actually:

ifeq ($(KBUILD_SRC),)

# OK, Make called in directory where kernel src resides
# Do we want to locate output files in a separate directory?
ifeq ("$(origin O)", "command line")
  KBUILD_OUTPUT := $(O)
endif

When you create the help target, the Makefile will run only that rule, and thus not recursively call itself, and therefore, KBUILD_SRC will not be set, and thus KBUILD_OUTPUT will remain unset.

John